
module IO_INPUT_SIM_tb;

    // Parameters

    //Ports
    reg  CLK;
    reg  RESET_n;
    reg  BTN;
    wire	[1:0] LED;
    wire [7:0] IO;
    reg [7:0] rIO;
    reg IO_input;
    initial
    begin
        CLK = 0;
        RESET_n = 0;
        BTN = 0;
        #10 RESET_n = 1;
        forever
        begin
            #5 CLK = ~CLK;
        end

    end

    initial begin
        #200 IO_input = 1;
        #200_000 rIO = 8'b00000010;
        #100_000 rIO = 8'b00000001;
        #100_000 rIO = 8'b00000010;
        #100_000 rIO = 8'b00000001;
    end

    assign IO = IO_input ? rIO : 8'bZZZZZZZZ;


    AHBLITE_SYS  AHBLITE_SYS_inst (
                     .CLK(CLK),
                     .RESET_n(RESET_n),
                     .BTN(BTN),
                     .LED(LED),
                     .IO(IO)
                 );

    //always #5  clk = ! clk ;

endmodule
